For transferring digital data between circuit elements the basic approaches of parallel and serial interfacing are available. A parallel interface consists of a number of parallel wired connections or lines so that a number of bit values may be transferred simultaneously by setting either the logical value “1” or the logical value “0” to each line, i.e. either setting or resetting each line simultaneously. A serial interface does not necessarily involve more than one data line on which the bit values are transferred sequentially by repeatedly either setting or resetting the data line.
The situation gets somewhat more complicated if the signal to be transmitted must conform to a certain higher-level structure, meaning that there are relatively long data sequences that must be handled independently from each other. In this patent application we will especially describe the transmission of digital image data over an interface. A digital image consists nearly always of a rectangular array of elementary picture elements or pixels. The image is read by scanning the horizontal lines formed by adjacent pixels in a prescribed order, usually from top to down and from left to right. In the resulting digital bit stream a predetermined number of bits describes the color of each pixel, the beginning of a line is indicated by a certain line synchronization or LSYNC signal and the beginning of a new image frame is indicated by a certain frame synchronization or FSYNC signal.
In order for the image transmission to function properly the transmitting device and the receiving device must share a common clock frequency for writing on and reading from the interfacing lines. Additionally the transmitting device must correctly convey the LSYNC and FSYNC signals to the receiving device in one way or another.
FIG. 1 illustrates a conventional parallel interface between a transmitting device 101 and a receiving device 102. The interface consists of a number of data lines, which are here numbered from 1 to N, a number of control lines and a clock line CLK. The number of control lines is shown to be M, and because we discuss especially the transmission of digital image data, among the control lines there are the synchronization lines FSYNC and LSYNC.
FIG. 2a illustrates schematically how the interface between devices 101 and 102 may be “serialized”. A parallel to serial (P/S) converter 201 is coupled to the parallel output of the transmitting device 101, and a corresponding serial to parallel (S/P) converter is coupled to the parallel input of the receiving device 102. A phase locked frequency multiplier 203 is utilized to multiply the frequency of the clock signal CLK coming from the transmitting device by N+M. The basic clock frequency CLK drives the parallel side of the P/S converter 201 and its N+M-multiplied version drives the serial side. Correspondingly a frequency divider 204 is used to restore the original CLK frequency at the receiving end so that the received N+M-multiplied clock frequency drives the serial side of the S/P converter and the original CLK frequency drives the parallel side. The original CLK frequency is also provided to the receiving device 102 for synchronizing the reading of the parallel input data. In addition to just converting the interface into serial form FIG. 2a illustrates how the immunity of the data and clock lines against common-mode interference may be enhanced by using differential transmitter-receiver pairs 205, 206 and 207, 208 respectively. For short differential transmission links e.g. between two integrated circuits within a single electronic apparatus it is commonplace to use so-called low-level differential transmitters and receivers so that the differential voltage levels appearing in the serial connection are well under the conventional +5V . . . −5V levels.
FIG. 2b illustrates the basic serial interface model where a transmitting device 251 needs only one connection to the receiving device 252. The transmitting device 251 comprises a multiplexer 253 that multiplexes the bits of the DATA, LSYNC and FSYNC digital signals into a common connecting line in the pace determined by a clock signal CLK. In the receiving device 252 there is a corresponding demultiplexer 254. In FIG. 2b the actual wired connection between the transmitting end and the receiving end is also shown to be differential, utilizing the differential transmitter 255 and the differential receiver 256. The LSYNC and FSYNC bit sequences that are multiplexed into the common connection must consist of bit patterns that are long enough so that their composition can be selected to be unique: when the demultiplexer 254 recognizes a certain predetermined pattern of consecutive bits in the received bitstream, it indicates that a synchronization signal has been received. We may refer to a number of consecutive bits as N, and denote the number of synchronization bits constituting the LSYNC and FSYNC patterns therein as M.
If the clock frequency of an interface is kept constant and not converted to higher values, a parallel interface is more effective in terms of throughput since N+M bits are transferred on each cycle of the basic clock frequency CLK. However, modern VLSI (Very Large Scale Integration) technology has made it possible to integrate so many different functions on a single semiconductor chip that the number of input and output lines to and from the chips has become a limiting factor. Serial interfaces do not need even nearly as many lines as parallel ones, which makes serializing an important aspect in modern circuit design.
The drawback of the arrangements of FIGS. 2a and 2b is that for a fraction M/(N+M) of the time the serial interfacing line is not transferring actual data or payload information, since it is used for transmitting control information. For example in FIG. 2a a feasible choice for values of M and N in practice could be M=2 and N=8, which would mean that only 80% of the active communication time is used for transmitting actual data. An additional drawback is the relatively high clock frequency, N+M times CLK, which is required to operate the converters and to time the transmission over the serial line(s). Usually the power consumption of converter devices is directly proportional to their operating frequency, and especially in small-sized portable electronic apparatuses all power consumption should be kept at minimum. Additionally a high clock frequency in a serial interface increases the amount of electromagnetig interference (EMI) caused to the surrounding circuitry.
The arrangements of FIGS. 2a and 2b is also susceptible to synchronization errors. The S/P converter in FIG. 2a is basically a parallel array of memory locations. A bit value is read from the serial line at each cycle of the multiplied clock frequency and written into a certain memory location. At the next cycle of the basic CLK frequency the data in the memory locations is latched into the parallel lines. If the writing started from an incorrect memory location, or if a distortion in the multiplied clock frequency line somehow erased one or more cycles of the multiplied clock frequency, the receiver may not get a correct result. The same applies if a bit is lost or inverted in the synchronization patterns required by the solution of FIG. 2b. 